1. Field of the Invention
The present invention releases a method for adjusting width of pulses through collecting information of a three-phase current, especially a method for adjusting width of pulses through collecting information of a three-phase current by a single DC-link current sensor.
2. Description of the Prior Art
Recently, accompanied with a boom in frequency-conversion technology, AC motors are becoming more and more important in many applications, such as machine tools, automobiles, or domestic frequency-conversion air-conditioners. In a driving system of an AC motor, the core technology of a DC/AC converter is based on pulse width modulation (PWM). Many technologies based on PWM have been developed further, such as sinusoidal pulse width modulation (SPWM), which compares voltages of a three-phase sinusoidal wave with those of a triangular chopped wave, and generates modulations according to the compared results. Due to an easy design and low noises and ripples, the SPWM is commonly applied in AC motor design. However, in a recent couple of years, another technology developed further from PWM, called space vector pulse width modulation (SVPWM), surpasses SPWM in many aspects. SVPWM utilizes the technology of controlling voltages of PWM through tracking a circular revolving magnetic field, and combining voltage space vectors to derive a track of magnetic flux linkage. SVPWM is capable of reducing harmonic waves of output currents, decreasing the power loss caused by harmonic waves in motors, and lowering torque pulses. SVPWM has advantages of low noise, high efficiency in voltage utilization, and being digitalized easily. Compared with SPWM, SVPWM can output more voltages at the same frequency, reduce switching times of transistors, and derive the relationship between a DC-link current and a phase current simply through outputted voltages generated according to the voltage space vectors. Therefore, application of SVPWM instead of SPWM in design of advanced motors is growing gradually.
In a close-loop control process, it's important for a three-phase AC motor to control the current loop properly to increase a bandwidth of the control loop. In the core technology of dominating an AC motor, how to adjust the output voltage of an inverter through a PWM signal, and further manage the current of the AC motor to generate a torque, and simultaneously govern the output torque effectively to get a better revolving efficiency of the AC motor are all based on how to control the current in three phases of the AC motor. Therefore, a driver of a general three-phase AC motor contains at least two phase-current sensors to get feedback current signals for arranging the current control loop. However, the at least two phase-current sensors (for example hall current sensors) increase the cost, volume, weight, and size of the circuitry. Moreover, because these two phase-current sensors only can sense current in two phases, the third phase current should be derived after estimation, and a great possibility of errors will occur in the estimation due to the characteristic differences between external circuitry components and level shifts. Once the errors were transferred to the output torque of the motor, a torque ripple will be produced as a result. Hence, some prior arts utilize a single DC-link current sensor to replace a plurality of phase-current sensors in order to solve this problem. Compared with the hall current sensors, the single DC-link current sensor is low-cost, light, and small, and through it, the wanted currents in three phases can be derived as well.
Methods of deriving currents in three phases from a single DC-link current sensor have been confined to the aforementioned SVPWM so far. However, applying the SPVWM method will face a problem that some voltage space vectors are so short that they are located in the immeasurable region, and are hard to be measured. For solving the problem, U.S. Pat. No. 6,735,537 B2 teaches moving the original voltage space vectors to produce long-enough voltage space vectors for measurement; however, these movements will not change the composite result of original voltage space vectors due to the balance between all the moved space vectors. Yet, this prior art gets disadvantages in a complicated realization way, and a difficulty in choosing timing for sampling current, which ought to be adjusted according to the moved displacement different from each time. Consequently, in this method, the measured phase current is not always the average phase current, and this mismeasurement will play a great influence on the current control of the motor.
Another article published in IEEE transactions on power electronics, Vol. 12, No. 6, November 1997, named “FPGA realization of space-vector PWM control IC for three-phase PWM inverters”, written by Ying-Yu Tzou and Hau-Jean Hsu, teaches that in a switching cycle, a zero vector is utilized to adjust the lengths of all the voltage space vectors for eliminating the problem caused by the voltage space vectors located in the immeasurable region. U.S. Pat. No. 7,102,327 B2 takes a further step from this theory to explain that the zero vector is chosen according to the lengths of the two main voltage space vectors. This method not only shrinks the immeasurable region, but also raises a solution of breaking each voltage space vector located in the immeasurable region into two composed vectors to get away from the immeasurable region so as to retrieve information of the three-phase current. However, the disadvantages of this method are complicated when realized, and a repeated counting in timing of sampling current needed in each cycle.
Applying SVPWM with inserting signals to decrease the immeasurable region is what was taught in U.S. Pat. No. 7,075,267 B1. U.S. Pat. No. 7,075,267 B1 indicates inserting a detecting vector in a PWM cycle to determine which phase current should be controlled in this cycle through the DC-link current measured through the detecting vector. Moreover, a hysteresis current controller is contained in circuitry for controlling the sinusoidal currents in three phases. However, this method is recommended to be applied in a system with a high switching frequency, in addition, the hysteresis current controller is an analog device, and not compatible with the digital circuitry of SVPWM. Furthermore, U.S. Pat. No. 7,015,664 B2 teaches to insert voltage space vectors to avoid the problem caused by the voltage space vector located in the immeasurable region. However, this method will influence the length of the composite voltage space vectors generated after combining the voltage space vectors of an SVPWM cycle, and the sampling frequency in a current loop. Another article published in IEEE transactions on power electronics, Vol. 21, No. 5, September 2006, named “Phase current reconstruction for AC motor drives using a DC-link signal current sensor and measurement voltage vectors”, written by Hongrae Kim and Thomas M. Jahns, teaches adding three detecting vectors with a sum of zero after the original SVPWM signal in a PWM cycle. This method will not be influenced by the immeasurable region at all when deriving the related information of the phase currents through the DC-link current, and is capable of lowering the switching frequency of PWM; however, it increases the switching times of transistors, and changes the length of the composite voltage space vector.
Besides, those techniques used in the prior art change the flowing direction of the measured DC-link current, meaning that the voltage on the DC-link current sensor switches between positive and negative values; therefore, the operational amplifier for amplifying the voltage on the DC-link current sensor should be chosen as a dual supply op amp instead of a single supply op amp, which is cheaper. Moreover, the system has to offer dual power sources additionally for the dual supply op amp. Therefore, the system becomes more complicated and costly. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional SVPWM system 200. SVPWM system 200 includes an input power source 3, a DC/AC converter 4, a control chip 8, a three-phase AC motor 5, a DC-link current-sensing resistor 6, a dual supply op amp 90, two voltage regulators 100 and 101, and an A/D converter 7. The DC/AC converter 4 further includes 6 power transistors S1, S2, S3, S4, S5, and S6. The input power source 3 coupled to the DC/AC converter 4 and the DC-link current-sensing resistor 6 is for supplying power to the DC/AC converter 4. The voltage regulator 101 coupled to the control chip 8 and the A/D converter 7 is for supplying power (for example +5V) to the control chip 8 and the A/D converter 7. The voltage regulator 100 coupled to the dual supply op amp 90 is for supplying dual power (for example +/−15V) to the dual supply op amp 90. The dual supply op amp 90 coupled to the DC-link current-sensing resistor 6 is for amplifying the voltage on the DC-link current-sensing resistor 6, and then outputting to the A/D converter 7. The DC-link current-sensing resistor 6 is coupled to the DC/AC converter 4, the current flowing through the DC-link current-sensing resistor 6 is the DC-link current transformed from currents in three phases. The three-phase AC motor 5 coupled to the DC/AC converter 4 is for supplying currents in three phases flowing in/out the DC/AC converter 4. The control chip 8 coupled to the A/D converter 7 and the voltage regulator 101 is for operating control algorithms and processing the feedback current signals. In addition, a majority of documents of the prior art adjust the width of pulses through collecting information of a three-phase current based on the SVPWM method; however, in most low-cost motors, the SPWM method instead of the SVPWM method is commonly applied, hence the techniques taught in a majority of documents of the prior art cannot be put in use in them.
Please refer to FIG. 3. FIG. 3 is a table of corresponding relationship between 8 voltage space vectors including two zero vectors V0(000) and V7(111), and 6 voltage space unit vectors V1(100), V2(110), V3(010), V4(011), V5(001), and V6(101), and the magnitude and direction of currents Ia, Ib, and Ic in three phases a, b, and c flowing through the DC-link current-sensing resistor 6. As shown in FIG. 1, “1” represents the upper arm of the power transistors S1, S3, and S5 being switched on, and the lower arm of the power transistors S2, S4, and S6 being switched off; on the contrary, “0” represents the upper arm of the power transistors S1, S3, and S5 being switched off, and the lower arm of the power transistors S2, S4, and S6 being switched on. For example, voltage space unit vector V1(100) represents the power transistors S1, S4, and S6 in the DC/AC converter 4 being switched on, and the power transistors S2, S3, and S5 being switched off. If the direction of current flowing into the three-phase AC motor 5 is set as positive, then the measured phase current flowing through the DC-link current-sensing resistor 6 is +Ia according to the voltage space unit vector V1(100). Please refer to FIG. 4, which illustrates the flowing direction of current +Ia. FIG. 4 is a diagram of flowing directions of a phase current and a DC-link current when the power transistors S1, S4, and S6 are switched on, and S2, S3, and S5 are switched off.
The 6 voltage space unit vectors V1˜V6 are mutually independent, and used as basic vectors in combining voltage space vectors, while the zero vectors V1 and V7 are used for adjusting the duty ratio. Please refer to FIG. 5. FIG. 5 is a diagram of a region of low modulation index in a voltage space vector drawing formed by the 6 voltage space unit vectors V1˜V6. In FIG. 5, the region formed by the voltage space vector V1(100) and V2(110) is called the first sextant, the region formed by the voltage space vector V2(110) and V3(010) is called the second sextant, and the rest may be deduced by analogy. Any voltage space vector can be formed by two of the 6 voltage space unit vectors V1˜V6 and the zero vector in a proper ratio. The length of each voltage space vector in FIG. 5 represents a period for a power transistor in FIG. 1 being switched-on. For example, V1(100) represents a cycle T in which the power transistors S1, S4, and S6 are switched on, and S2, S3, and S5 are switched off.
If a voltage space vector located between voltage space unit vectors V1 and V2, the optimal switching sequence of this vector is V0, V1, V2, V7, V2, V1, V0 according to the SVPWM theory, therefore, in each cycle, a DC-link current, from which information of phase currents can be collected, is produced theoretically. However in fact, when the voltage space vector is located in the region of low modulation index (the region of slashes in FIG. 5), or located in the edges of active vector regions (the region of slashes in FIG. 7), the voltage space vector itself is too short, in other words, the period for the power transistor being switched-on is so short that the current flowing through the power transistor has not reached a steady state for sampling, then the power transistor is switched off again. Therefore the current flowing through the DC-link current-sensing resistor fails to be sampled in these conditions. FIG. 7 is a diagram of the edges of active vector regions in a voltage space vector drawing formed by the 6 voltage space unit vectors V1˜V6. The region of low modulation shown in FIG. 5 and the edges of active vector regions shown in FIG. 7 are jointly called “immeasurable regions”. Please refer to FIG. 6. FIG. 6 illustrates a cycle of a voltage space vector located in the region of low modulation (the region of slashes in FIG. 5). In FIG. 6, when “A” signal is “1”, it shows that the power transistors S1 is switched on and the power transistor S2 is switched off; when “A” signal is “0”, it represents that the power transistors S1 is switched off and the power transistor S2 is switched on; when “B” signal is “1”, it shows that the power transistors S3 is switched on and the power transistor S4 is switched off; when “B” signal is “0”, it represents that the power transistors S3 is switched off and the power transistor S4 is switched on; when “C” signal is “1”, it shows that the power transistors S5 is switched on and the power transistor S6 is switched off; when “C” signal is “0”, it represents that the power transistors S5 is switched off and the power transistor S6 is switched on. From FIG. 6, we can see that this voltage space vector is located between voltage space unit vectors V1 and V2, therefore it could follow the optimal switching sequence V0(000), V1(100), V2(110), V7(111), V2(110), V1(100), V0(000) derived from the SVPWM theory. And as aforementioned, the length of the voltage space vector is very short, hence a long period in the cycle of this voltage space vector is full with the zero vector V7(111). Moreover, being located between V1 and V2, this voltage space vector can be composed by V1 and V2 in a certain ratio. In FIG. 6, the vector in time span T1/2 is V1(100), the vector in time span T2/2 is V2(110); we can see time of both these two vectors is very short (it means the lengths of these two vectors are very short), and cannot meet the minimum sampling time span (Tm+Td) for a PWM system. Hence these two vectors lead to a failure in current sampling. Wherein the sampling time span Tm is related to the time period for a transistor from being switched on to a steady state, the op-amp slew rate (inversely proportional to transition time for an op amp to be switched from a low voltage to a high voltage), and the sampling time of an A/D converter; Td is related to the transition time for power transistors of the upper and lower arms being switched-on and cut-off.
Similarly, FIG. 8 illustrates a cycle of a voltage space vector located in the edges of the active vector region (the region of slashes in FIG. 7). In FIG. 8, “A”, “B”, and “C” signals represent the same meanings as in FIG. 6, therefore the descriptions of them are omitted here for the sake of brevity. The voltage space vector in FIG. 8 is also located between voltage space unit vectors V1 and V2, can be composed by V1 and V2 in a certain ratio, and is suitable for applying the optimal switching sequence V0, V1, V2, V7, V2, V1, V0 according to the SVPWM theory. Because this voltage space vector is located in the edges of active vector region, this vector is composed by a longer voltage space vector V1 (in FIG. 8, V1 represents the vector in the time span T1/2, and T1/2>=Tm+Td), and a short voltage space vector V2 (in FIG. 8, V2 represents the vector in the time span T2/2, and T2/2<=Tm+Td). As a result, only V1 vector can be sampled, V2 fails in the sampling process due to a too short length.